I have been waiting for someone to put a real number on the idea that NAND might sit next to accelerators the way HBM does, and Sandisk and SK hynix finally did. On August 3 and 4, 2026, the two companies released the first High Bandwidth Flash technical specification through the Open Compute Project. The consortium itself started in February 2026. The pitch is blunt. Stack NAND high enough, wire it with a UCIe interconnect, and give inference workloads a near-compute memory tier that is denser and non-volatile in a way HBM never was. Capacity targets go up to 512GB through 8-Hi and 16-Hi stacks. Bandwidth grades land roughly between 0.4 TB/s and 3.0 TB/s. That is not a press-deck fantasy range. It is the opening public envelope for a memory class the industry has been talking around for years.
What HBF actually claims on paper
High Bandwidth Flash is being sold as a NAND-based alternative and complement to HBM, not a drop-in replacement for every training cluster. The capacity story is the easy sell. Up to 512GB in 8-Hi and 16-Hi NAND stacks is a different conversation from the HBM packages that already dominate board real estate and BOM cost. Bandwidth grades from about 0.4 TB/s to 3.0 TB/s matter more for people who actually size KV caches and embedding tables. Those are the workloads that choke when you cannot keep the working set close to the GPU or custom ASIC.
The interconnect choice is UCIe. That detail is doing a lot of work. If HBF is going to live as near-compute memory for AI inference, it has to speak the same packaging language the rest of the advanced package world is converging on. GPU and CPU integration is the stated target, not a vague cloud storage story. I read that as an admission that the interesting fight is on the package and the board, not in a remote SSD shelf.
Sandisk's press went out August 3. SK hynix followed August 4. The timing around FMS 2026 in Santa Clara was not subtle. Flash Memory Summit has become the place where storage vendors try to sound like AI infrastructure companies, and this week they had a real specification to point at instead of a concept slide. Google and Tenstorrent joining the consortium gives the effort a customer and an accelerator house with skin in the game.
Samples of the memory are expected in the second half of 2026. AI devices that use it are eyed for early 2027. That timeline is aggressive for a first public spec, and it should be treated as a product roadmap claim, not a shipping guarantee. Still, a public OCP document changes the conversation. Vendors can argue about pinouts and firmware. They cannot pretend the category does not exist.
I keep coming back to the non-volatile part. HBM is fast and expensive and empty when you cut power. HBF is being positioned as the thing you keep model weights, large embeddings, and inference-side state on without paying DRAM prices for every gigabyte. Whether that works in practice depends on latency behavior the first spec will not fully settle for me until silicon is in a lab. Capacity and peak bandwidth are the opening argument. Endurance, QoS under random access, and controller complexity are the fights still ahead.
Why inference teams should care before training teams do
The consortium began in February 2026, which means this August release is the first public milestone after half a year of closed work. That is fast for a memory standard that wants OCP legitimacy. It also tells you the buyers pushing this are not waiting for another HBM cycle. Inference economics are ugly when every token path needs more HBM than the board can afford. A denser flash tier next to the compute die is an obvious place to hunt for relief.
I am skeptical of any claim that one new memory class fixes the AI memory crunch. I am not skeptical that people will try. Google's presence in the consortium matters because Google has already lived through every generation of TPU packaging politics. Tenstorrent's presence matters because custom silicon shops feel HBM scarcity differently from hyperscalers with preferential supply. When both show up, the spec is not a two-vendor science project.
The bandwidth grades matter for different product shapes. A 0.4 TB/s class device is a different animal from a 3.0 TB/s stack. One might land in edge inference boxes or cost-constrained accelerators. The other is chasing something closer to HBM-class movement for selected traffic. The useful question for architects is not whether HBF is faster than HBM. It is which bytes never needed HBM in the first place.
Near-compute memory for inference is the cleanest use case in the materials. Keep the hot path on HBM or local SRAM. Park the fat, mostly read, often reused tensors on HBF. That is the story I expect vendors to tell through 2027. Training shops will watch, because anything that loosens package constraints eventually shows up in their BOM meetings, but the first devices are being aimed at inference.
OCP publication also matters for everyone who is tired of proprietary memory islands. If HBF stays an open technical specification path, accelerator vendors can design against a shared envelope instead of waiting for a private NDA stack from one supplier. That is the optimistic reading. The pessimistic reading is that first silicon still ships through the usual preferred-customer funnel, and the open part arrives later for everyone else.
What I will watch through early 2027
The sample window in H2 2026 is the first real test. Specs are cheap. Controllers, firmware, and package yield are not. If Sandisk and SK hynix miss that sample window, the early-2027 AI device talk gets soft fast. If they hit it, every GPU and ASIC roadmap slide that currently ends at HBM suddenly needs a second column.
I also want clearer statements about where HBF sits relative to HBM in a real system. Complement is the honest word in the briefing materials. Replacement is the word marketers will eventually try. Higher capacity and non-volatility are genuine differentiators. Latency and write behavior will decide whether software teams treat HBF as a first-class memory tier or as a fast local store with awkward semantics.
FMS 2026 gave the announcement a stage. The quieter work starts now in OCP working groups, package partners, and the first accelerator teams willing to redesign a board around a new stack. Google and Tenstorrent are early signals, not a full customer list. Watch who shows up next. Memory standards live or die on second-wave adopters.
For developers and platform teams, the practical takeaway today is simple. The industry is no longer pretending HBM alone can carry AI memory demand. A NAND-based high-bandwidth tier is now a published technical target with named suppliers, an OCP path, a UCIe integration story, and a date range for samples. That alone is enough to put HBF on architecture review agendas for 2027 systems.
I do not need HBF to dethrone HBM to call this week important. I need it to prove that near-compute flash can take a real share of inference working sets without turning into another overpromised storage tier. August 3 and 4 gave us the first public yardstick. The next twelve months will tell us whether that yardstick was ambition or a product.
